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4- and 8-channel 15 v/+12 v multiplexers ADG1308/adg1309 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features 33 v supply range 130 ? on resistance fully specified at 15 v/+12 v 3 v logic-compatible inputs rail-to-rail operation break-before-make switching action 16-lead tssop and 16-lead soic_n upgrade for the adg508a / adg509a applications audio and video routing test equipment data acquisition systems battery-powered systems communication systems signal routing functional block diagrams ADG1308 s1 s8 d adg1309 s1a s4b da db s4a s1b 1-of-4 decoder 1-of-8 decoder a0 a1 en a0 a1 a2 en 06009-001 figure 1. general description the ADG1308 and adg1309 are monolithic analog multi- plexers consisting of eight single channels and four differential channels, respectively. the ADG1308 switches one of eight inputs to a common output as determined by the 3-bit binary address lines a0, a1, and a2. the adg1309 switches one of four differential inputs to a common differential output as determined by the 2-bit binary address lines a0 and a1. an en input on both devices is used to enable or disable the device. when disabled, all channels are switched off. when the switches are on, each switch conducts equally well in both directions and has an input signal range that extends to the power supplies. in the off condition, signal levels up to the supplies are blocked. all switches exhibit break-before-make switching action for use in multiplexer applications. inherent in the design is the low charge injection for minimum transients when switching the digital inputs. fast switching speed coupled with high signal bandwidth makes the parts suitable for video signal switching. cmos construction ensures ultra low power dissipation, making the parts ideally suited for portable and battery-powered instruments. product highlights 1. 16-lead tssop and 16-lead soic_n available. 2. pin compatible with the adg508akr and the adg509akr devices. 3. 3 v, logic-compatible digital input where: v ih = 2.0 v and v il = 0.8 v. 4. v l logic power supply not required. 5. low power consumption.
ADG1308/adg1309 rev. 0 | page 2 of 16 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagrams............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 dual supply ................................................................................... 3 single supply ................................................................................. 5 absolute maximum ratings............................................................ 6 esd caution...................................................................................6 pin configurations and function descriptions ............................7 ADG1308 truth table ..................................................................7 adg1309 truth table ..................................................................8 typical performance characteristics ..............................................9 test circuits..................................................................................... 11 terminology .................................................................................... 13 outline dimensions ....................................................................... 14 ordering guide .......................................................................... 14 revision history 4/06revision 0: initial version
ADG1308/adg1309 rev. 0 | page 3 of 16 specifications dual supply v dd = +15 v 10%, v ss = C15 v 10%, gnd = 0 v, unless otherwise noted. 1 table 1. parameter +25oc ? 40oc to +105oc unit test conditions/comments analog switch analog signal range v ss to v dd v on resistance, r on 130 typ v s = 10 v, i s = ?1 ma; see figure 13 210 300 max v dd = +13.5 v, v ss = ?13.5 v on resistance match between channels, ?r on 5 typ v s = 10 v, i s = ?1 ma 10 max on resistance flatness, r flat (on) 25 typ v s = ?5 v, 0 v, +5 v, i s = ?1 ma 70 max leakage currents source off leakage, i s (off ) 1 na typ v d = 10 v, v s = ?10 v; see figure 14 50 na max drain off leakage, i d (off ) 1 na typ v s = 1 v, 10 v; v d = 10 v, 1 v; see figure 14 50 na max channel on leakage, i d, i s (on) 1 na typ v s = v d = 10 v; see figure 15 50 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.005 a max v in = v inl or v inh 0.1 a max digital input capacitance, c in 5 pf typ dynamic characteristics 2 transition time, t transition 80 ns typ r l = 300 , c l = 35 pf 130 190 ns max v s = 10 v; see figure 16 t on (en) 80 ns typ r l = 300 , c l = 35 pf 100 120 ns max v s = 10 v; see figure 18 t off (en) 85 ns typ r l = 300 , c l = 35 pf 100 150 ns max v s = 10 v; see figure 18 break-before-make time delay, t bbm 25 ns typ r l = 300 , c l = 35 pf 10 ns min v s1 = v s2 = 10 v; see figure 17 charge injection 2 pc typ v s = 0 v, r s = 0 , c l = 1 nf; see figure 19 off isolation 80 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 20 channel-to-channel crosstalk 80 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 21 ?3 db bandwidth 500 mhz typ r l = 50 , c l = 5 pf; see figure 22 c s (off ) 5 pf typ f = 1 mhz, v s = 0 v c d (off) ADG1308 15 pf typ f = 1 mhz, v s = 0 v adg1309 10 pf typ f = 1 mhz, v s = 0 v c d , c s (on) ADG1308 20 pf typ f = 1 mhz, v s = 0 v adg1309 15 pf typ f = 1 mhz, v s = 0 v
ADG1308/adg1309 rev. 0 | page 4 of 16 parameter +25oc ? 40oc to +105oc unit test conditions/comments power requirements v dd = +16.5 v, v ss = ?16.5 v i dd 0.002 a typ digital inputs = 0 v or v dd 1.0 a max i dd 220 a typ digital inputs = 5 v 320 a max i ss 0.002 a typ digital inputs = 0 v or v dd or 5 v 1.0 a max v dd /v ss 5/16.5 v min/v max |v dd | = |v ss | 1 temperature range for b ve rsion is C40c to +105c. 2 guaranteed by design; not subject to production test.
ADG1308/adg1309 rev. 0 | page 5 of 16 single supply v dd = 12 v, v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. 1 table 2. parameter +25oc ?40oc to +105oc unit test conditions/comments analog switch analog signal range 0 to v dd v on resistance, r on 325 typ v s = 0 v to 10 v, i s = ?1 ma; see figure 13 500 660 max v dd = 10.8 v, v ss = 0 v on resistance match between channels, ?r on 10 typ v s = 0 v to 10 v, i s = ?1 ma 20 max on resistance flatness, r flat (on) 65 typ v s = 3 v, 6 v, 9 v, i s = ?1 ma leakage currents v dd = 13.2 v source off leakage, i s (off ) 1 na typ v s = 1 v/10 v, v d = 10 v/1 v; see figure 14 50 na max drain off leakage, i d (off ) 1 na typ v s = 1 v/10 v, v d = 10 v/1 v; see figure 14 50 na max channel on leakage, i d, i s (on) 1 na typ v s = v d = 1 v or 10 v; see figure 15 50 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.001 0.1 a max v in = v inl or v inh digital input capacitance, c in 3 pf typ dynamic characteristics 2 transition time, t transition 100 ns typ r l = 300 , c l = 35 pf 170 240 v s = 8 v; see figure 16 t on (en) 90 ns typ r l = 300 , c l = 35 pf 110 170 v s = 8 v; see figure 18 t off (en) 105 ns typ r l = 300 , c l = 35 pf 130 180 v s = 8 v; see figure 18 break-before-make time delay, t bbm 45 ns typ r l = 300 , c l = 35 pf 20 ns min v s1 = v s2 = 8 v; see figure 17 charge injection 2 pc typ v s = 6 v, r s = 0 , c l = 1 nf; see figure 19 off isolation 80 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 20 channel-to-channel crosstalk 80 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 21 ?3 db bandwidth 500 mhz typ r l = 50 , c l = 5 pf; see figure 22 c s (off ) 5 pf typ f = 1 mhz, v s = 6 v c d (off) ADG1308 10 pf typ f = 1 mhz, v s = 6 v adg1309 15 pf typ f = 1 mhz, v s = 6 v c d , c s (on) ADG1308 20 pf typ f = 1 mhz, v s = 6 v adg1309 15 pf typ f = 1 mhz, v s = 6 v power requirements v dd = 13.2 v i dd 0.002 a typ digital inputs = 0 v or v dd 1.0 a max i dd 220 a typ digital inputs = 5 320 a max v dd 5/16.5 v min/v max v ss = 0 v, gnd = 0 v 1 temperature range for the b version is C40c to +105c. 2 guaranteed by design; not subject to production test.
ADG1308/adg1309 rev. 0 | page 6 of 16 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter rating v dd to v ss 35 v v dd to gnd ?0.3 v to +25 v v ss to gnd +0.3 v to ?25 v analog, digital inputs v ss ? 0.3 v to v dd + 0.3 v or 30 ma (whichever occurs first) 1 continuous current, s or d pins 30 ma 100 ma peak current, s or d pins (pulsed at 1 ms, 10% duty cycle maximum) operating temperature range industrial (b version) C40c to +105c storage temperature range C65c to +150c junction temperature 150c 112c/w tssop, ja , thermal impedance 77c/w 16-lead soic, ja , thermal impedance 260 (+0/?5)c reflow soldering peak temperature (pb-free) 1 overvoltages at a, en, s, or d pins are clamped by internal diodes. current should be limited to the maximum ratings provided. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd pr ecautions are recommended to avoid performance degradation or loss of functionality.
ADG1308/adg1309 rev. 0 | page 7 of 16 pin configurations a nd function descriptions 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 en v ss s1 s4 s3 s2 a0 a2 gnd v dd s7 ds s6 s5 a1 ADG1308 top view (not to scale) 8 0 6009-002 figure 2. ADG1308 pin configuration (tssop and soic_n) table 4. ADG1308 pin function descriptions pin number mnemonic description 1 a0 logic control input a0. 2 en active high digital input. when low, the device is disabled and all switches are off. when high, ax logic inputs determine on switches. 3 v ss most negative power supply potential. in single supply applications, this pin can be connected to ground. 4 s1 source terminal 1. can be an input or an output. 5 s2 source terminal 2. can be an input or an output. 6 s3 source terminal 3. can be an input or an output. 7 s4 source terminal 4. can be an input or an output. 8 d drain terminal. can be an input or an output. 9 s8 source terminal 8. can be an input or an output. 10 s7 source terminal 7. can be an input or an output. 11 s6 source terminal 6. can be an input or an output. 12 s5 source terminal 5. can be an input or an output. 13 v dd most positive power supply potential. 14 gnd ground (0 v) reference. 15 a2 logic control input a2. 16 a1 logic control input a1. ADG1308 truth table table 5. a2 a1 a0 en on switch x x 1 1 x 1 0 none 0 0 0 1 1 0 0 1 1 2 0 1 0 1 3 0 1 1 1 4 1 0 0 1 5 1 0 1 1 6 1 1 0 1 7 1 1 1 8 1 1 x = dont care.
ADG1308/adg1309 rev. 0 | page 8 of 16 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 en v ss s1a s4a s3a s2a a0 gnd v dd s1b s4b da db s3b s2b a1 adg1309 top view (not to scale) 0 6009-003 figure 3. adg1309 pin configuration (tssop and soic_n) table 6. adg1309 pin function descriptions pin number soic/tssop mnemonic description 1 a0 logic control input a0. 2 en active high digital input. when low, the device is disabled and all switches are off. when high, ax logic inputs determine on switches. 3 v ss most negative power supply potential. in single supply applications, this pin can be connected to ground. 4 s1a source terminal 1a. can be an input or an output. 5 s2a source terminal 2a. can be an input or an output. 6 s3a source terminal 3a. can be an input or an output. 7 s4a source terminal 4a. can be an input or an output. 8 da drain terminal a. can be an input or an output. 9 db drain terminal b. can be an input or an output. 10 s4b source terminal 4b. can be an input or an output. 11 s3b source terminal 3b. can be an input or an output. 12 s2b source terminal 2b. can be an input or an output. 13 s1b source terminal 1b. can be an input or an output. 14 v dd most positive power supply potential. 15 gnd ground (0 v) reference. 16 a1 logic control input a1. adg1309 truth table table 7. al a0 en on switch pair x 0 none 1 1 x 0 0 1 1 0 1 1 2 1 0 1 3 1 1 1 4 1 x = dont care.
ADG1308/adg1309 rev. 0 | page 9 of 16 typical performance characteristics v dd = +15v v ss = ?15v source or drain voltage (v) on resistance ( ? ) 200 180 160 140 120 100 60 80 0 20 40 ?15 ?12 ?9 ?6 ?3 3 9 061 21 source or drain voltage (v) on resistance ( ? ) 600 400 500 300 200 0 100 024681012 v dd = 12v v ss = 0v t a = +25c t a = +85c t a = ?40c 0 6009-007 5 t a = 25c 0 6009-004 figure 4. on resistance as a function of v d (v s ) for dual supply figure 7. on resistance as a function of v d (v s ) for different temperatures, single supply source or drain voltage (v) on resistance ( ? ) 450 400 350 300 250 150 200 0 50 100 024681012 v dd = 12v v ss = 0v t a = 25c 0 6009-005 v s (v) charge injection (pc) 6 4 2 0 ?2 ?4 ?6 ?15 ?10 ?5 0 15 10 5 v dd = +15v v ss = ?15v v dd = +12v v ss = 0v v dd = +5v v ss = ?5v t a = 25 c 06009-008 figure 5. on resistance as a function of v d (v s ) for single supply figure 8. charge injection vs. source voltage source or drain voltage (v) on resistance ( ? ) 250 150 200 0 50 100 ?15 ?10 ?5 0 5 10 15 v dd = +15v v ss = ?15v t a = +25c t a = +85c t a = ?40c 0 6009-006 temperature (c) time (ns) 160 140 120 100 80 60 20 40 0 ?40 ?20 0 20 60 40 80 t on t off v dd = +15v v ss = ?15v 06009-009 figure 6. on resistance as a function of v d (v s ) for different temperatures, dual supply figure 9. t on /t off time vs. temperature
ADG1308/adg1309 rev. 0 | page 10 of 16 frequency (hz) off isol a tion (db) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 10k 100k 1m 10m 100m 1g v dd = +15v v ss = ?15v t a = 25c 06009-010 frequency (hz) crosstalk (db) ? 10 ?20 ?30 ?40 ?50 ?60 ?90 ?80 ?70 ?100 10k 100k 1m 10m 100m 1g sxa ? sxb s1x ? s2x v dd = +15v v ss = ?15v t a = 25c 06009-011 figure 10. off isol ation vs. frequency figure 12. crosstalk vs. frequency v bias (v) capacitance (pf) 12 0 ?15 15 ?10 ?5 0 5 10 10 8 6 4 2 source/drain on drain off source off v dd = +15v v ss = ?15v t a = 25c 06009-012 figure 11. ADG1308 capacitance vs. source voltage, 15 v dual supply
ADG1308/adg1309 rev. 0 | page 11 of 16 test circuits sd v s a a v d i s (off) i d (off) 06009-014 i ds sd v s v 0 6009-013 sd a v d i d (on) nc nc = no connect 06009-015 figure 14. off leakage figure 15. on leakage figure 13. on resistance 3v 0v output t r < 20ns t f < 20ns address drive (v in ) t transition t transition 50% 50% 90% 90% output ADG1308 1 a0 a1 a2 50? 300? gnd s1 s2?s7 s8 d 35pf v in 2.4v en v dd v ss v dd v ss v s1 v s8 1 similar connection for adg1309. 06009-016 figure 16. address to ou tput switching times, t transition output ADG1308 1 a0 a1 a2 50 ? 300 ? gnd s1 s2?s7 s8 d 35pf v in 2.4v en v dd v ss v dd v ss v s 1 similar connection for adg1309. 3v 0v output 80% 80% a ddress drive (v in ) t bbm 06009-017 figure 17. break-before-make delay, t bbm output ADG1308 1 a0 a1 a2 50 ? 300? gnd s1 s2?s8 d 35pf v in en v dd v ss v dd v ss v s 1 similar connection for adg1309. 3v 0v output 50% 50% t off (en) t on (en) 0.9v o 0.9v o enable drive (v in ) 06009-018 figure 18. enable delay, t on (en), t off (en)
ADG1308/adg1309 rev. 0 | page 12 of 16 3v v in v out q inj = c l v out v out d s en gnd c l 1nf v out v in r s v s v dd v ss v dd v ss a0 a1 a2 ADG1308 1 1 similar connection for adg1309. 06009-019 figure 19. charge injection v out 50? network analyzer r l 50? s d 50? off isolation = 20 log v out v s v s v dd v ss 0.1f v dd 0.1f v ss gnd 06009-020 v out 50? network analyzer r l 50 ? s d insertion loss = 20 log v out with switch v out without switch v s v dd v ss 0.1f v dd 0.1f v ss gnd 06009-021 figure 20. off isolation figure 22. bandwidth channel-to-channel crosstalk = 20 log v out gnd s1 d s2 v out network analyzer r l 50? r 50? v s v s v dd v ss 0.1f v dd 0.1f v ss 06009-022 figure 21. channel-to-channel crosstalk
ADG1308/adg1309 rev. 0 | page 13 of 16 terminology r on ohmic resistance between d and s. r on difference between the r on of any two channels. i s (off) source leakage current when the switch is off. i d (off) drain leakage current when the switch is off. i d , i s (on) channel leakage current when the switch is on. v d (v s ) analog voltage on terminal d and terminal s. c s (off) channel input capacitance for off condition. c d (off) channel output capacitance for off condition. c d , c s (on) on switch capacitance. c in digital input capacitance. t on (en) delay time between the 50% and 90% points of the digital input and switch on condition. t off (en) delay time between the 50% and 90% points of the digital input and switch off condition. t transition delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. t bbm off time measured between the 80% point of both switches when switching from one address state to another. v inl maximum input voltage for logic 0. v inh minimum input voltage for logic 1. i inl (i inh ) input current of the digital input. i dd positive supply current. i ss negative supply current. off isolation a measure of unwanted signal coupling through an off channel. charge injection a measure of the glitch impulse transferred from the digital input to the analog output during switching. bandwidth the frequency at which the output is attenuated by 3 db. on response the frequency response of the on switch.
ADG1308/adg1309 rev. 0 | page 14 of 16 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 23. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-ac 16 9 8 1 4.00 (0.1575) 3.80 (0.1496) 10.00 (0.3937) 9.80 (0.3858) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2283) seating plane 0.25 (0.0098) 0.10 (0.0039) 0.51 (0.0201) 0.31 (0.0122) 1.75 (0.0689) 1.35 (0.0531) 8 0 0.50 (0.0197) 0.25 (0.0098) 1.27 (0.0500) 0.40 (0.0157) 0.25 (0.0098) 0.17 (0.0067) coplanarity 0.10 45 figure 24. 16-lead standard small outline package [soic_n] narrow body (r-16) dimensions shown in millimeters and (inches) ordering guide model temperature range package description package option ? 40c to +105c ADG1308bruz 16-lead thin shrink small outline package [tssop] ru-16 1 ? 40c to +105c ADG1308bruz-reel7 1 16-lead thin shrink small outline package [tssop] ru-16 ? 40c to +105c ADG1308brz 1 16-lead narrow body small outline package [soic_n] r-16 ? 40c to +105c ADG1308brz-reel7 16-lead narrow body small outline package [soic_n] r-16 1 ? 40c to +105c adg1309bruz 1 16-lead thin shrink small outline package [tssop] ru-16 ? 40c to +105c adg1309bruz-reel7 1 16-lead thin shrink small outline package [tssop] ru-16 ? 40c to +105c adg1309brz 16-lead narrow body small outline package [soic_n] r-16 1 ? 40c to +105c adg1309brz-reel7 16-lead narrow body small outline package [soic_n] r-16 1 1 z = pb-free part.
ADG1308/adg1309 rev. 0 | page 15 of 16 notes
ADG1308/adg1309 rev. 0 | page 16 of 16 notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06009-0-4/06(0)

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